串接子模組

f50e6196 · tonytsai · 6dfcd5b4 · f50e6196 · f50e6196 · 0300357f
Commit f50e6196 authored Apr 22, 2020 by tonytsai
Hide whitespace changes
Inline Side-by-side

Showing with 10 additions and 0 deletions

.gitmodules .gitmodules +3 -0

.idea/vcs.xml .idea/vcs.xml +6 -0

sample/pythonsubmodule sample/pythonsubmodule +1 -0

No files found.
--- a/.gitmodules
+++ b/.gitmodules
+[submodule "sample/pythonsubmodule"]
+	path = sample/pythonsubmodule
+	url = http://gitlab.epurplevineip.com/tonytsai/pythonsubmodule
--- a/.idea/vcs.xml
+++ b/.idea/vcs.xml
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="VcsDirectoryMappings">
+    <mapping directory="$PROJECT_DIR$" vcs="Git" />
+  </component>
+</project>
\ No newline at end of file
--- a/pythonsubmodule @ 0300357f
+++ b/pythonsubmodule @ 0300357f
+Subproject commit 0300357f31241ef5facab054c1ed41733f2a9710